Data encoding schemes are commonly used in serial interfaces, such as a Fiber Channel Arbitrated Loop (FCAL), a Serial Attached Small Computer Standard Interface (SCSI), and a serial ATA (SATA) interface. Many different encoding schemes and codes can be used. One common code used for serial interfaces is a byte-oriented DC-balanced (0,4) run length limited, rate 8B/10B partitioned block transmission code. One form of an 8B/10B encoder/decoder is described in U.S. Pat. No. 4,486,739 granted Dec. 4, 1984 for “Byte Oriented DC Balanced (0,4) 8B/10B Partitioned Block Transmission Code” by Franaszek et al. The Franaszek 8B/10B encoder/decoder partitions an 8-bit input word into a 5-bit portion and a 3-bit portion. The 5-bit portion is encoded to a 6-bit output, and the 3-bit portion is encoded with a control bit to a 4-bit output.
Run length is defined as the number of identical contiguous symbols (ones or zeros) that appear in a data stream. A large number of contiguous binary ones will produce a highly positive DC signal, whereas a large number of contiguous binary zeros will produce a highly negative DC signal. However, it is important to maintain DC balance in the signal, both in long data strings as well as short data strings. Thus, on a (0,4) code, a symbol is followed by no more than four contiguous identical symbols (meaning a data stream may contain a string of up to five identical symbols before one of opposite value). The “0” in the (0,4) notation means that a symbol may be followed by no less than zero contiguous identical symbols—meaning that any given symbol may be followed by a symbol of same or opposite value. The (0,4) code disclosed in the Franaszek et al. patent permits only four characters that might generate five identical contiguous symbols, three of those characters being special characters. Hence, except for those four characters, the (0,4) code disclosed in the Franaszek et al. patent is effectively a (0,3) code.
The disparity of a block of data is the difference between the numbers of ones and zeros in the block. To adjust the DC level of the output string, the Franaszek et al. apparatus compares the running disparity from prior words to the disparity of the current word portion being encoded. The encoder then produces the output word portion, or a complement thereof. For example, if the running disparity is +1 and the current output word portion has a disparity of +2, the output portion is complemented to a word portion with a disparity of −2 and a −1 disparity is passed to the next encoding stage. The maximum disparity possible in the Franaszek et al. scheme is +3 and −3, and the disparity at the bounds between the 6-bit output and 4-bit output portions is either +1 or −1. Since the Franaszek et al. encoder is designed so a zero disparity is not possible, the disparity at the bounds between the 6-bit and 4-bit portions is at the minimum values of ±1.
In the Franaszek et al. scheme, the running disparity is passed from one encoding stage to the next, so that the running disparity from the 5B/6B encoder stage is held to encode the 3-bit input portion for the same word in the 3B/4B stage, and the running disparity from the 3B/4B encoder stage is held to encode the 5-bit input portion of the next word in the 5B/6B encoder stage. The holding of the running disparity between the stages required the two encoder stages be operated during different portions of the clock cycle. The output registers therefore are operated on separate portions of the clock.
To achieve wider data paths, a parallel version of the Franaszek 8B/10B encoder was implemented. In the parallel version, one of two 8B/10B encoders encoded the upper half of a 16-bit input word while the other 8B/10B encoder encoded the lower half of the 16-bit word. The disparity was passed in sequence so that the running disparity of the upper 6-bit word portion was passed to the upper 3B/4B encoder, the running disparity of the upper 4-bit word portion was passed to the lower 5B/6B encoder, the running disparity of the lower 6-bit word portion was passed to the lower 3B/4B encoder, and the running disparity of the lower 4-bit word portion was passed to the upper 5B/6B encoder for the next word. To avoid holding each of the running disparities one-half cycle as in the original Franaszek et al. design, the parallel design operated the encoders and buffers on the same clock cycle and held the running disparity of the lower 4-bit word portion for later encoding in the upper 5B/6B encoder. The disparity of the upper 6-bit word portion was combinationally passed to the upper 3B/4B encoder, the disparity of the upper 4-bit word portion was combinationally passed to the lower 5B/6B encoder, and the disparity of the lower 6-bit word portion was combinationally passed to the upper 3B/4B encoder. Hence, during a single clock cycle, the running disparity of the second 4-bit output sub-block of a previous word is combined with the disparity of the current first 6-bit output sub-block and the running disparity of both current 6-bit output sub-blocks and the current first 4-bit output sub-block are combined with the disparities of both current 4-bit output sub-blocks and the current second 6-bit output sub-block, thereby selectively complementing all output sub-blocks for a current data block during a single clock cycle.
U.S. Pat. No. 5,663,724 discloses a binary encoding apparatus for producing a DC balanced run length limited rate 16B/20B code from an unconstrained input data stream that includes consecutive 16-bit data blocks. The encoding apparatus includes a pair of parallel 8B/10B encoders each having a 5B/6B and a 3B/4B encoder portion responsive to respective 5-bit and 3-bit sub-blocks to produce respective 6-bit and 4-bit output sub-blocks. Each encoder portion is responsive to the disparity of its current output sub-block and a running disparity associated with another sub-block to selectively complement the bits of its sub-block to reduce running disparity. The encoder further includes disparity processing means for combinationally passing the running disparity of each 6-bit output sub-block to the 3B/4B encoder of the associated 8B/10B encoder and the running disparity of the 4-bit output sub-block associated with a first of the 8B/10B encoders to the 5B/6B encoder of a second of the 8B/10B encoders, thereby selectively complementing the 4-bit output sub-blocks and the 6-bit output sub-block associated with the second 8B/10B encoder for a current data block. The disparity processing means additionally holds and processes the running disparity of the 4-bit output sub-block associated with the second 8B/10B encoder to the 5B/6B encoder of the first 8B/10B encoder, thereby selectively complementing the 6-bit output sub-block associated with the first 8B/10B encoder for the next data block. In one embodiment, the encoder apparatus further implements a forced disparity control. The forced disparity control responds to a special character bit and a forced disparity bit to force the running disparity of the 5B/6B encoder of the first, upper encoder to a selected polarity. The forced disparity control also passes the running disparity of the selected polarity of the immediately prior 4-bit output sub-block of the second, lower 8B/10B encoder to the 5B/6B encoder of the first 8B/10B encoder.
The 8B/10B encoders and decoders described above are highly combinational circuits with many levels of logic. The serial interfaces in which these encoders and decoders are used continue to support higher and higher interface speeds over time. As the interface speeds increase, it is becoming more difficult to meet timing margins in the integrated circuits that implement the serial interface logic.
In the 8B/10B encoding schemes discussed above, the running disparity from the upper 8B/10B encoder is calculated and passed combinationally to the lower 8B/10B encoder. The running disparity from the upper 8B/10B encoder is required before the lower 8B/10B encoder can evaluate its 10-bit output. The combinational path from the upper encoder to the lower encoder is becoming increasing more difficult to evaluate in a single clock cycle as the interface speeds increase with the integrated circuit technologies available today.
The conventional approach of increasing bandwidth through the encoder by widening the encoder from an 8B/10B encoding scheme to a 32B/40B encoding scheme and running the encoder at a high clock speed does not solve the problem. There is still a serial path from the uppermost 8B/10B encoder through the middle 8B/10B encoders to the lowermost 8B/10B encoder.
Improved encoders and encoding schemes are therefore desired for codes, such as 8B/10B codes, that constrain the running disparity in symbols produced by the code.